RISC-V International announced the approval of the first four specifications and extensions in 2022 – RISC-V Efficient Trace (E-Trace), RISC-V Supervisor Binary Interface (SBI), the RISC-V Unified Extensible Firmware Interface (UEFI) specification, and the RISC-V Zmmul pure multiply extension.
RISC-V announced the approval of these new specifications at Embedded World. It is reported that RISC-V International will also hold a member company innovation pavilion in the exhibition hall before June 23. Currently, 16 specifications of RISC-V representing more than 40 extensions have been ratified.
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Calista Redmond, CEO of RISC-V, said: “RISC-V’s contribution and collaborative culture continue to yield impressive strategic results, and RISC-V members are leaders in the age of open computing, proving that collaboration accelerates innovation through shared investment, while increasing global opportunities.”
“These new specifications accelerate the design of embedded and large systems where debugging is one of the hardest things to do on a chip,” said Mark Himelstein, CTO of RISC-V. “RISC-V’s E-Trace creates a standard The processor trace mode, which is extremely efficient, is particularly useful in embedded system design.
ISC-V SBI provides a similar key resource for developers. The ability to port supervisor mode software across all RISC-V implementations essentially allows Developers to write code once and apply it everywhere.”
The SBI of the RISC-V specification architectures the firmware layer between the hardware platform and the operating system kernel, using the application binary interface in supervisor mode (S-mode or VS-mode). This abstraction enables all RISC-V operating system implementations to have common platform services.
Many RISC-V members have implemented the RISC-V SBI specification in their RISC-V solutions, so ratification of the specification will ensure a standard approach across the RISC-V ecosystem, ensuring compatibility. The development and approval of the specification were led by Atish Patra of Rivos, working on a platform-level steering committee.
Himelstein also explained: “For many MCU applications, the frequency of division operations is too low to justify the cost of divider hardware, and the RISC-V Zmmul extension would be particularly beneficial for simple FPGA soft cores.”
RISC-V Zmmul Multiply Only implements a low-cost implementation that requires multiplication operations but not division and is part of the RISC-V Unprivileged Specification. Development and approval of the extension were led by Allen Baum, whose work was carried out on a non-privileged ISA committee.
