Samsung launches new semiconductor packaging task force

Samsung Electronics has just launched a Semiconductor Packaging Task Force/Team (TF). The team, led directly by the Samsung CEO, aims to strengthen cooperation with large foundry customers in the chip packaging space.

According to businesskorea, Samsung Electronics’ DS division set up the team in mid-June, directly under the DS division representative Jing Guixian (sound). The team consists of DS Division Test and System Package (TSP) engineers, semiconductor R&D center researchers, and various executives from the memory and foundry divisions. The team hopes to propose advanced chip packaging solutions and strengthen cooperation with major customers.

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Packaging refers to cutting the wafers that have completed the front-end process into semiconductor shapes or wiring, also known as the “back-end process”. To put it simply, the integrated circuit die (Die) produced by the foundry is placed on a substrate that acts as a carrier, and then the pins are drawn out, and then fixed, and packaged as a whole. It can play the role of protecting the chip, which is equivalent to the shell of the chip, which can not only fix and seal the chip but also enhance its electrical and thermal performance.

Today, as the miniaturization of circuits in the front-end process reaches its limit, large semiconductor manufacturers have proposed the so-called “3D packaging” or “chiplet” technology, which is similar to connecting different small chips in parallel to make them operate as a single chip. At the same time, the cost is greatly reduced, which has attracted the attention of the industry.

Currently, a group of global semiconductor giants including Intel and TSMC is actively investing in advanced packaging technology. In 2022, Intel and TSMC will account for 32% and 27% of global advanced packaging investment, respectively, according to market research firm Yole Development. Samsung Electronics ranked fourth after Taiwan’s back-end processing company ASE.

Moreover, Intel launched a 3D packaging technology called “Foveros” in 2018 and announced that the technology will be applied to various new products, such as “Lakefield” chips.

In addition, TSMC recently decided to use its advanced packaging technology to produce AMD’s latest processors. Both Intel and TSMC have also actively established 3D packaging research centers in Japan, which have been operating since June 24.

It is worth mentioning that Samsung Electronics also launched the 3D overlay technology “X-Cube” in 2020. Choi Si-young, president of Samsung Electronics’ foundry division, said last year that “3.5D packaging” technology was being developed. The semiconductor industry is currently curious about whether Samsung Electronics’ task force can find a way to fight or even stay ahead of its competitors in the field.